(1) Field of the Invention
The present invention relates to a ferro-electric memory device having ferro-electric capacitors, and in particular to a ferro electric memory device with an improved retention characteristic.
(2) Description of the Related Art
In recent years, with the refinement and increase in capacity of the memory cells which constitute a ferro-electric memory device, the sizes of the memory cells in the ferro-electric memory device have become small. As the result, the sizes of ferro-electric capacitors have also been decreased, and thus the electric charge amounts have also been decreased. After that, the following is becoming important: how to secure sufficient amounts of electric charges to be read out and to increase the electric potential difference to be amplified by a sense amplifier, that is, the difference in electric potentials to be read out from the ferro-electric capacitors.
Here, the configuration of a ferro-electric memory device in a conventional embodiment will be described with reference to figures (for example, refer to Reference 1: Japanese Laid-Open Patent Application No. 2003-59251).
As shown in FIG. 1, the ferro-electric memory device 10 has 2T2C type memory cells which are arranged in an m×n array. More specifically, the ferro-electric memory device 10 includes: normal cells MC11 to MCmn; normal cells XMC11 to XMCmn; normal cell plate drivers CPD1 to CPDn; reference cells RMC1 to RMCm; reference cells XRMC1 to XRMCm; a reference cell plate driver RCPD; sense amplifiers SA1 to SAm; a power supply VDD; a control circuit 11; a temperature detection circuit 12 and the like.
Hereinafter, the suffix “i” represents an integer of 1 to m, and the suffix “1-m” represents all the integers of 1 to m. Likewise, the suffix “j” represents an integer of 1 to n, and the suffix “1-n” represents all the integers of 1 to n.
Note that 2T2C type memory cells are made up of a pair of 1T1C type memory cells in which complementary data is written. Here is an example case where data is written in the memory cell which is made up of a normal cell MCmn and a normal cell XMCmn. When data “1” is written in the normal cell MCmn through a bit line BLm, data “0” is written in the XMCmn through a bit line XBLm. After that, in the case where the data is read out, the difference between the potential corresponding to the data “1” and the potential corresponding to the data “0” which are read out through the bit line BLm and the bit line XBLm is amplified by the sense amplifier SAm.
The respective normal cell MC[i][j] and normal cell XMC[i][j] are 1T1C type memory cells.
The normal cell MC[i][j] includes a normal cell transistor T[i][j] and a normal cell ferro-electric capacitor C[i][j]. Likewise, the normal cell XMC[i][j] includes a normal cell transistor XT[i][j] and a normal cell ferro-electric capacitor XC[i][j].
The normal cell plate driver CPD[J] supplies a voltage to be applied to the ferro-electric capacitors C[1-m][j] and XC[1-m][j] which are connected to the normal cell plate line CP[j] using the voltage to be supplied from the power supply VDD which is a source.
The respective reference cells RMC[i] and XRMC[i] are 1T1C type memory cells.
The reference cell RMC[i] includes a reference cell transistor RT[i] and a reference cell ferro-electric capacitor RC[i]. Likewise, the reference cell XRMC[i] includes a reference cell transistor XRT[i] and a reference cell ferro-electric capacitor XRC[i].
The reference cell plate driver RCPD supplies a voltage to be applied to the reference cell ferro-electric capacitors RC[i] and XRC[i] which are connected to the reference cell plate line RCP using the voltage to be supplied from the power supply VDD which is a source.
The sense amplifier SA[i] amplifies the difference in the potential corresponding to the data which has been read out through the bit line BL[i] and the potential corresponding to the data which has been read out through the bit line XBL[i].
The power supply VDD supplies the voltage vdd to the normal cell plate drivers CPD[1-n] and the reference cell plate driver RCPD.
The control circuit 11 controls the respective normal cell plate drivers CPD[1-n] and a reference cell plate driver RCPD, and drives the respective normal cell plate lines CP[1-n] and the reference cell plate line RCP.
More specifically, the control circuit 11 is connected to (a) the respective normal cell plate driver CPD[j], normal cells MC[1-m][j] and normal cells XMC[1-m][j] through a normal cell word line WL[j]. In addition, the control circuit 11 is connected to (b) the respective normal cell plate drivers CPD[1-n] through the normal cell plate line CP0. In addition, the control circuit 11 is connected to (c) the respective reference cell plate driver RCPD, reference cells RMC[1-m] and reference cells XRMC[1-m] through the reference cell word line RWL. Further, the control circuit 11 is connected to (d) the reference cell plate driver RCPD through the reference cell plate line RCP0.
After that, the control circuit 11 supplies a Hi signal to the respective normal cell plate drivers CPD[1-n] through the normal cell plate line CP0 in the case of driving the normal cell plate line CP[j]. In addition, the control circuit 11 supplies a Hi signal to the normal cell plate driver CPD[j] through the normal cell word line WL[j]. On the other hand, the control circuit 11 supplies a Hi signal to the reference cell plate driver RCPD through the reference cell plate line RCP0 in the case of driving the reference cell plate line RCP. In addition, the control circuit 11 supplies a Hi signal to the reference cell plate driver RCPD through the reference cell word line RWL.
The temperature detection circuit 12 detects a temperature and supplies, to the control circuit 11, a control signal S for switching the time for supplying the Hi signal from a first duration to a second duration which is longer than the first duration when the detected temperature is below a predetermined temperature or below.
However, the ferro-electric memory device in the conventional embodiment lengthens the duration of voltage application to the ferro-electric capacitors in order to suppress the deterioration of the retention characteristics when an ambient temperature has decreased. As the result, there emerges a problem that a much longer cycle time is required.